The present invention relates generally to wireless signal processing, and, in particular, to a frequency locked feedback loop for wireless communications.
Currently available wireless communication systems can incorporate well over one hundred (or more) distinct frequency channels. Frequency tuning functions to select frequency channels typically tune to a single frequency in an attempt to match a single filter peak. Tuning functions, such as phase locked loops (PLLs), often perform tuning fairly close to the filter peak.
PLLs typically operate on a feedback loop mechanism that attempts to minimize the phase difference between a target signal and an adjustable signal, thereby phase aligning the two signals. While PLLs can be effective, they have a number of shortcomings. For example, a PLL can unintentionally lock onto harmonics of the target frequency, rather than the target frequency itself. PLLs can suffer from common phase-noise and susceptibility to jitter and skew, known as “skitter”. Capture, lock, and voltage fluctuations may destabilize PLLs. Additionally, PLLs typically rely on a single point solution, where a control circuit attempts to drive phase-error to a null or zero value, which can increase the chance of a false lock while also requiring a continuous reference clock to maintain a lock and generate an output frequency. PLLs and other frequency tuning functions typically cannot be used to align with the valley between two filter peaks.